This invention relates to delay line time compressors, generally referred to as deltics, and more particularly to an improved deltic which can be selectively operated at different speed-up ratios and hence may be termed a universal deltic.
There exists a need for such a universal deltic for use in connection with a spectrum analyzer which is designed to operate on signals multiplied by a factor M of up to 96,240 from the baseband or real time source signals. In one such frequency analyzer system the baseband signals are recorded on tape and played back at a multiplication factor M.sub.1 of 240 from the baseband. The universal deltic, inserted between the tape machine and the spectrum analyzer, would be required to provide a factor M.sub.2 of 401 to render the desired maximum factor of 96,240, M being equal to the product of M.sub.1 and M.sub.2. When vernier operation is desired at a speed-up ratio of 240:1, M.sub.2 would be increased to 1203, and M.sub.1 would be left at 240, whereby M would be increased to 3.times.96,240, and the bandwidth of the signal at the deltic input would be reduced by a factor of three. If real-time operation were desired, the input signal would be fed directly to the deltic, reducing M.sub.1 to unity, and increasing M.sub.2 to 96,240. Since the analyzer concerned can process the same number of frequency resolution elements/sec. in the real-time mode as in the nonreal-time mode, it could be time-shared between 240 real-time channels. From the foregoing, it will be apparent that there exists a need for a universal deltic, the multiplication factor or ratio M of which can be selectively varied. Now, the general arrangement and use of deltic recirculation loops for the purpose of permitting the processing of data at rates faster than real time is well known. Such arrangements are useful in connection with the input of data to a spectrum analyzer, for example, as discussed in U.S. Pat. No. 2,958,039 of V. C. Anderson.
Briefly, a deltic with a multiplication ratio of M is a device which takes amplitude samples (spaced incremental time units apart) of an input waveform and stores them closer together in a delay line memory D seconds in length. Since a given baseband input S seconds in length is reduced by a factor of M to D seconds, a spectrum analyzer can "look" at the deltic output M times before a given time-record is completely replaced in the delay line by new input data. Hence, time compression allows one spectrum analyzer to process many discrete frequencies in the time that would otherwise have been consumed to process one.
The delay line portion of a conventional deltic may comprise either a device such as an N-bit glass delay line operating on ultrasonic propagation, or a device such as an N-bit shift register. A simple conventional deltic using an N-bit shift register comprises a sample gate connected to introduce sample pulses or bits into a recirculation loop consisting of the shift register and an inhibit gate. The shift register is operated at a clock determined bit rate of F.sub.c Hz and has an overall delay of D seconds. The sample and inhibit gates are used to allow a sample pulse, occurring at a rate of F.sub.s Hz, to replace the oldest bit in the shift register with a new bit of information from an analog to digital converter every time the information in the loop makes n recirculations. The simplest such deltic results when n=1 and new information is inserted in the loop every N+1 clock intervals. Since EQU M=F.sub.c /F.sub.s, (Eq. 1)
the multiplication for n=1 is given by EQU M=N+1. (Eq. 2)
For n.gtoreq.1, the multiplication is given by EQU M=nN+1. (Eq. 3)
It is, of course, necessary to make n&gt;1 when the input sampling period is greater than the delay line length, D.
In a more general, well known form of deltic, provision is made for inserting k bits of information into the loop every n recirculations of the memory record. To this end, a buffer store is used to collect k-1 of the k bits to be inserted in the loop. The kth bit is available on line at the analog to digital converter output. A parallel-to-serial converter puts parallel bits at the buffer store output into the delay line sequentially. The multiplication, M, for the general deltic is given by EQU M=nN+k/k (Eq. 4)
or EQU M=nN/k+1. (Eq. 5)
From Eq. 5, it is apparent that M can be varied by changing either n, N, or k. It is not desirable to vary k, since the length of the two registers and the repetition rate of one control pulse would have to be altered. It would be preferable to vary n. However, if n is increased by a factor of three, for example, as would be necessary for the earlier mentioned vernier operation, the multiplication M does not increase by precisely a factor of three.